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? semiconductor components industries, llc, 2001 may, 2001 rev. 5 1 publication order number: mc74ac259/d mc74ac259, mc74act259 8-bit addressable latch the mc74ac259/74act259 is a highspeed 8bit addressable latch designed for general purpose storage applications in digital systems. it is a multifunctional device capable of storing single line data in eight addressable latches, and also a 1of8 decoder and demultiplexer with active high outputs. the device also incorporates an active low common clear for resetting all latches, as well as an active low enable. it is functionally identical to the als259 8bit addressable latch. ? serialtoparallel conversion ? eight bits of storage with output of each bit available ? random (addressable) data entry ? active high demultiplexing or decoding capability ? easily expandable ? common clear 15 16 14 13 12 11 10 2 1 34567 v cc 9 8 mr e dq 7 q 6 q 5 q 4 a 0 a 1 a 2 q 0 q 1 q 2 q 3 gnd figure 1. pinout: 16lead packages conductors (top view) a 0 a 1 a 2 ed mr q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 figure 2. logic symbol mode select table e mr mode l h addressable latch h h memory l l active high 8channel demultiplexer h l clear h = high voltage level l = low voltage level http://onsemi.com dip16 n suffix case 648 1 16 so16 d suffix case 751b 1 16 device package shipping ordering information mc74ac259n pdip16 25 units/rail mc74ac259d soic16 48 units/rail mc74ac259dr2 2500 tape & reel tssop16 dt suffix case 948f mc74ac259dt tssop16 96 units/rail mc74ac259dtr2 tssop16 soic16 2500 tape & reel mc74act259n pdip16 25 units/rail mc74act259d soic16 48 units/rail mc74act259dr2 2500 tape & reel mc74act259dt tssop16 96 units/rail mc74act259dtr2 tssop16 soic16 2500 tape & reel 1 16 see general marking information in the device marking section on page 8 of this data sheet. device marking information 1 16 eiaj16 m suffix case 966 mc74ac259m eiaj16 50 units/rail
mc74ac259, mc74act259 http://onsemi.com 2 mode selectfunction table operating inputs outputs operating mode mr e d a 0 a 1 a 2 q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 master reset l h x x x x l l l l l l l l l l d l l l q = d l l l l l l l demultiplex l ldhll l q = dllllll demultiplex (active high l ldlhl l lq = dlllll (active high decoder when ? ????? ? ??????? d eco d er w h en d = h ) ? ????? ? ??????? d = h) ? ????? ? ??????? l l dhhh l llllllq = d store h h x x x x q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 store (do nothing) h h x x x x q 0 q 1 q 2 q 3 q 4 q 5 q 6 q 7 h l d l l l q = d q 1 q 2 q 3 q 4 q 5 q 6 q 7 h ldhll q 0 q = d q 2 q 3 q 4 q 5 q 6 q 7 addressable h ldlhl q 0 q 1 q = d q 3 q 4 q 5 q 6 q 7 add ressa bl e latch ? ????? ? ??????? latch w wwwww w wwwwwww w wwwww w wwwwwww h l d h h h q 0 q 1 q 2 q 3 q 4 q 5 q 6 q = d h = high voltage level l = low voltage level x = immaterial d = high or low data one setup time prior to the lowtohigh enable transition q = lower case letters indicate the state of the referenced output established during the last cycle in which it was addressed or cleared. functional description the mc74ac259/74act259 has four modes of operation as shown in the mode selection table. in the addressable latch mode, data on the data line (d) is written into the addressed latch. the addressed latch will follow the data input with all nonaddressed latches remaining in their previous states in the memory mode. all latches remain in their previous state and are unaffected by the data or address inputs. in the oneofeight decoding or demultiplexing mode, the addressed output will follow the state of the d input with all other outputs in the low state. in the clear mode all outputs are low and unaffected by the address and data inputs. when operating the mc74ac/act259 as an addressable latch, changing more than one bit of the address could impose a transient wrong address. therefore, this should only be done while in the memory mode. the mode select function table summarizes the operations of the mc74ac/act259.
mc74ac259, mc74act259 http://onsemi.com 3 mr a 2 a 1 a 0 d e q 7 q 6 q 5 q 4 q 3 q 2 q 1 q 0 note: this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays. figure 3. logic diagram
mc74ac259, mc74act259 http://onsemi.com 4 maximum ratings* symbol parameter value unit v cc dc supply voltage (referenced to gnd) 0.5 to +7.0 v v in dc input voltage (referenced to gnd) 0.5 to v cc +0.5 v v out dc output voltage (referenced to gnd) 0.5 to v cc +0.5 v i in dc input current, per pin 20 ma i out dc output sink/source current, per pin 50 ma i cc dc v cc or gnd current per output pin 50 ma t stg storage t emperature 65 to +150 c *maximum ratings are those values beyond which damage to the device may occur. functional operation should be restricted to the recom- mended operating conditions. recommended operating conditions symbol parameter min typ max unit v supply voltage ac 2.0 5.0 6.0 v v cc supply voltage act 4.5 5.0 5.5 v v in , v out dc input voltage, output voltage (ref. to gnd) 0 v cc v v cc @ 3.0 v 150 t r , t f input rise and fall time (note 1) ac devices exce p t schmitt in p uts v cc @ 4.5 v 40 ns/v r , f ac devices except schmitt inputs v cc @ 5.5 v 25 tt f input rise and fall time (note 2) v cc @ 4.5 v 10 ns/v t r , t f in ut rise and fall time (note 2) act devices except schmitt inputs v cc @ 5.5 v 8.0 ns/v t j junction temperature (pdip) 140 c t a operating ambient temperature range 40 25 85 c i oh output current high 24 ma i ol output current low 24 ma 1. v in from 30% to 70% v cc ; see individual data sheets for devices that differ from the typical input rise and fall times. 2. v in from 0.8 v to 2.0 v; see individual data sheets for devices that differ from the typical input rise and fall times.
mc74ac259, mc74act259 http://onsemi.com 5 dc characteristics 74ac 74ac symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 3.0 1.5 2.1 2.1 v out = 0.1 v g input v oltage 4.5 2.25 3.15 3.15 v or v cc 0.1 v 5.5 2.75 3.85 3.85 v il maximum low level 3.0 1.5 0.9 0.9 v out = 0.1 v input v oltage 4.5 2.25 1.35 1.35 v or v cc 0.1 v 5.5 2.75 1.65 1.65 v oh minimum high level 3.0 2.99 2.9 2.9 i out = 50 m a g output voltage 4.5 4.49 4.4 4.4 v 5.5 5.49 5.4 5.4 *v in = v il or v ih 3.0 2.56 2.46 v 12 ma 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 24 ma v ol maximum low level 3.0 0.002 0.1 0.1 i out = 50 m a output voltage 4.5 0.001 0.1 0.1 v 5.5 0.001 0.1 0.1 *v in = v il or v ih 3.0 0.36 0.44 v 12 ma 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 24 ma i in maximum input 55 01 10 m a v i =v cc gnd leakage current 5.5 0 . 1 1 . 0 m a v i = v cc , gnd i old 2minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 m a v in =v cc or gnd q supply current 5.5 8 . 0 80 m a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one output loaded at a time. note: i in and i cc @ 3.0 v are guaranteed to be less than or equal to the respective limit @ 5.5 v v cc .
mc74ac259, mc74act259 http://onsemi.com 6 ac characteristics (for figures and waveforms see section 3 of the on semiconductor fact data book, dl138/d) 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 3.3 2.0 9.0 14.5 1.5 17.0 ns 3 5 t plh d n to q n 5.0 2.0 6.5 10.0 1.5 11.5 ns 3 5 t phl propagation delay 3.3 2.0 9.0 13.5 1.5 16.0 ns 3 5 t phl d n to q n 5.0 2.0 6.0 9.5 1.5 11.0 ns 3 5 t plh propagation delay 3.3 2.0 10.5 15.0 1.5 17.5 ns 3 6 t plh e to q n 5.0 2.0 7.0 10.5 1.5 12.5 ns 3 6 t phl propagation delay 3.3 2.0 8.0 12.5 1.5 15.0 ns 3 6 t phl e to q n 5.0 2.0 7.5 9.0 1.5 11.0 ns 3 6 t plh propagation delay 3.3 2.0 12.0 19.0 1.5 22.5 ns 3 6 t plh address to q n 5.0 2.0 8.0 13.0 1.5 15.5 ns 3 6 t phl propagation delay 3.3 2.0 10.0 16.0 1.5 19.0 ns 3 6 t phl address to q n 5.0 2.0 7.0 11.0 1.5 13.0 ns 3 6 t phl propagation delay 3.3 2.0 8.0 12.0 1.5 13.5 ns 3 7 t phl mr to q 5.0 2.0 6.0 9.0 1.5 10.0 ns 3 7 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v. ac operating requirements 74ac 74ac symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 3.3 3.5 4.5 ns 39 t s d n to e 5.0 2.5 3.5 ns 3 9 t h hold time, high or low 3.3 2.5 2.5 ns 39 t h d n to e 5.0 2.0 2.0 ns 3 9 t s setup time 3.3 7.0 9.0 ns 36 t s address to e 5.0 4.0 6.0 ns 3 6 t h hold time 3.3 2.0 2.0 ns 36 t h address to e 5.0 2.0 2.0 ns 3 6 t w minimum pulse 3.3 6.0 6.5 ns 36 t w width m r 5.0 5.5 6.0 ns 3 6 t w minimum pulse 3.3 6.5 7.0 ns 36 t w width e 5.0 5.5 6.0 ns 3 6 *voltage range 3.3 v is 3.3 v 0.3 v. *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac259, mc74act259 http://onsemi.com 7 dc characteristics 74act 74act symbol parameter v cc (v) t a = +25 c t a = 40 c to +85 c unit conditions typ guaranteed limits v ih minimum high level 4.5 1.5 2.0 2.0 v v out = 0.1 v g input v oltage 5.5 1.5 2.0 2.0 v or v cc 0.1 v v il maximum low level 4.5 1.5 0.8 0.8 v v out = 0.1 v input v oltage 5.5 1.5 0.8 0.8 v or v cc 0.1 v v oh minimum high level 4.5 4.49 4.4 4.4 v i out = 50 m a g output voltage 5.5 5.49 5.4 5.4 v *v in = v il or v ih 4.5 3.86 3.76 v i oh 24 ma 5.5 4.86 4.76 i oh 24 ma v ol maximum low level 4.5 0.001 0.1 0.1 v i out = 50 m a output voltage 5.5 0.001 0.1 0.1 v *v in = v il or v ih 4.5 0.36 0.44 v i ol 24 ma 5.5 0.36 0.44 i ol 24 ma i in maximum input 55 01 10 m a v i =v cc gnd leakage current 5.5 0 . 1 1 . 0 m a v i = v cc , gnd d i cct additional max. i cc /input 5.5 0.6 1.5 ma v i = v cc 2.1 v i old 2minimum dynamic ot tc t 5.5 75 ma v old = 1.65 v max i ohd output current 5.5 75 ma v ohd = 3.85 v min i cc maximum quiescent 55 80 80 m a v in =v cc or gnd q supply current 5.5 8 . 0 80 m a v in = v cc or gnd *all outputs loaded; thresholds on input associated with output under test. 2maximum test duration 2.0 ms, one output loaded at a time. ac characteristics (for figures and waveforms see section 3 of the on semiconductor fact data book, dl138/d) 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. min typ max min max t plh propagation delay 50 20 65 11 0 15 12 5 ns 35 t plh pro agation delay d n to q n 5. 0 2 . 0 6 .5 11 . 0 1 .5 12 .5 ns 3 5 t phl propagation delay 50 20 70 10 5 15 12 0 ns 35 t phl pro agation delay d n or q n 5. 0 2 . 0 7. 0 10 .5 1 .5 12 . 0 ns 3 5 t plh propagation delay 50 20 10 5 14 0 15 16 5 ns 36 t plh pro agation delay e to q n 5. 0 2 . 0 10 .5 14 . 0 1 .5 16 .5 ns 3 6 t phl propagation delay 50 20 90 12 0 15 14 0 ns 36 t phl pro agation delay e or q n 5. 0 2 . 0 9 . 0 12 . 0 1 .5 14 . 0 ns 3 6 t plh propagation delay 50 20 80 11 5 15 13 5 ns 36 t plh pro agation delay address to q n 5. 0 2 . 0 8 . 0 11 .5 1 .5 13 .5 ns 3 6 t phl propagation delay 50 20 60 10 0 15 12 0 ns 36 t phl pro agation delay address to q n 5. 0 2 . 0 6 . 0 10 . 0 1 .5 12 . 0 ns 3 6 t phl propagation delay 50 20 10 0 15 11 0 ns 37 t phl pro agation delay mr to q 5. 0 2 . 0 10 . 0 1 .5 11 . 0 ns 3 7 *voltage range 5.0 v is 5.0 v 0.5 v.
mc74ac259, mc74act259 http://onsemi.com 8 ac operating requirements 74act 74act symbol parameter v cc * (v) t a = +25 c c l = 50 pf t a = 40 c to +85 c c l = 50 pf unit fig. no. typ guaranteed minimum t s setup time, high or low 50 30 40 ns 39 t s setu time, high or low d n to e 5. 0 3 . 0 4 . 0 ns 3 9 t h hold time, high or low 50 25 25 ns 39 t h hold time, high or low d n to e 5. 0 2 .5 2 .5 ns 3 9 t s setup time 50 45 65 ns 36 t s setu time address to e 5. 0 4 .5 6 .5 ns 3 6 t h hold time 50 25 25 ns 36 t h hold time address to e 5. 0 2 .5 2 .5 ns 3 6 t w minimum pulse 50 70 75 ns 36 t w width mr 5. 0 7. 0 7.5 ns 3 6 t w minimum pulse 50 70 75 ns 36 t w width e 5. 0 7. 0 7.5 ns 3 6 *voltage range 5.0 v is 5.0 v 0.5 v. capacitance symbol parameter value typ unit test conditions c in input capacitance 4.5 pf v cc = 5.0 v c pd power dissipation capacitance 50.0 pf v cc = 5.0 v marking diagrams a = assembly location wl, l = wafer lot yy, y = year ww, w = work week ac259 awlyww mc74ac259n awlyyww ac 259 alyw act259 awlyww act 259 alyw mc74act259n awlyyww dip16 so16 tssop16 eiaj16 74ac259 alyw
mc74ac259, mc74act259 http://onsemi.com 9 package dimensions notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of leads when formed parallel. 4. dimension b does not include mold flash. 5. rounded corners optional. a b f c s h g d j l m 16 pl seating 18 9 16 k plane t m a m 0.25 (0.010) t dim min max min max millimeters inches a 0.740 0.770 18.80 19.55 b 0.250 0.270 6.35 6.85 c 0.145 0.175 3.69 4.44 d 0.015 0.021 0.39 0.53 f 0.040 0.70 1.02 1.77 g 0.100 bsc 2.54 bsc h 0.050 bsc 1.27 bsc j 0.008 0.015 0.21 0.38 k 0.110 0.130 2.80 3.30 l 0.295 0.305 7.50 7.74 m 0 10 0 10 s 0.020 0.040 0.51 1.01 pdip16 n suffix 16 pin plastic dip package case 64808 issue r notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019 so16 d suffix 16 pin plastic soic package case 751b05 issue j
mc74ac259, mc74act259 http://onsemi.com 10 package dimensions tssop16 dt suffix 16 pin plastic tssop package case948f01 issue o ??? ??? dim min max min max inches millimeters a 4.90 5.10 0.193 0.200 b 4.30 4.50 0.169 0.177 c --- 1.20 --- 0.047 d 0.05 0.15 0.002 0.006 f 0.50 0.75 0.020 0.030 g 0.65 bsc 0.026 bsc h 0.18 0.28 0.007 0.011 j 0.09 0.20 0.004 0.008 j1 0.09 0.16 0.004 0.006 k 0.19 0.30 0.007 0.012 k1 0.19 0.25 0.007 0.010 l 6.40 bsc 0.252 bsc m 0 8 0 8 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a does not include mold flash. protrusions or gate burrs. mold flash or gate burrs shall not exceed 0.15 (0.006) per side. 4. dimension b does not include interlead flash or protrusion. interlead flash or protrusion shall not exceed 0.25 (0.010) per side. 5. dimension k does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the k dimension at maximum material condition. 6. terminal numbers are shown for reference only. 7. dimension a and b are to be determined at datum plane -w-. section nn seating plane ident. pin 1 1 8 16 9 detail e j j1 b c d a k k1 h g detail e f m l 2x l/2 u s u 0.15 (0.006) t s u 0.15 (0.006) t s u m 0.10 (0.004) v s t 0.10 (0.004) t v w 0.25 (0.010) 16x ref k n n eiaj16 m suffix 16 pin plastic eiaj package case96601 issue o h e a 1 dim min max min max inches --- 2.05 --- 0.081 millimeters 0.05 0.20 0.002 0.008 0.35 0.50 0.014 0.020 0.18 0.27 0.007 0.011 9.90 10.50 0.390 0.413 5.10 5.45 0.201 0.215 1.27 bsc 0.050 bsc 7.40 8.20 0.291 0.323 0.50 0.85 0.020 0.033 1.10 1.50 0.043 0.059 0 0.70 0.90 0.028 0.035 --- 0.78 --- 0.031 a 1 h e q 1 l e 10 0 10 l e q 1 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions d and e do not include mold flash or protrusions and are measured at the parting line. mold flash or protrusions shall not exceed 0.15 (0.006) per side. 4. terminal numbers are shown for reference only. 5. the lead width dimension (b) does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) total in excess of the lead width dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. minimum space between protrusions and adjacent lead to be 0.46 ( 0.018). m l detail p view p c a b e m 0.13 (0.005) 0.10 (0.004) 1 16 9 8 d z e a b c d e e l m z
mc74ac259, mc74act259 http://onsemi.com 11 notes
mc74ac259, mc74act259 http://onsemi.com 12 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into t he body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc74ac259/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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